This invention relates to a semiconductor IC device with redundancy circuits and more particularly to such a circuit with which a redundancy circuit can be replaced in an improved manner.
The yield of semiconductor IC circuits, and more particularly semiconductor memory devices, usually drops as they are miniaturized in order to increase their capacity. Their yield also drops as the manufacturing process becomes complicated or the chip size is increased. One of the methods of preventing such a drop in the yield has been to provide inside each memory chip not only the usual set of components such as bit lines, bit line selection lines, word lines, memory cells, row decoders, bit line selection circuits and column decoders, but also what is frequently refererd to as redundancy circuits comprising reserve bit lines, etc. such that, when a defect is found in the original set of components, such a defective component can be replaced by the reserve component. A certain percentage of what would otherwise be deemed a defective chip can be rescued by using a redundancy circuit in this manner. When a defect is discovered and it is decided to make use of a redundancy circuit, a polysilicon fuse or the like is usually cut by melting to inactivate the row decoder or column decoder containing the address of the defective bit. At the same time, the address of the defect must be programmed into the reserve row decoder or column decoder.
With reference to FIG. 2 which shows a dynamic RAM as an example of semiconductor memory device having a redundancy circuit, AB indicates an address bus, CDEC0 through CDEC2 are original (not redundant) column decoders, CDECR is a reserve (redundant) column decoder, SL0 through SL2 and SR0 through SR2 are original bit line selection circuits, SLR and SRR are reserve bit line selection circuits, BSL0 through BSL2 and BSR0 through BSR2 are original bit line selection lines, BSLR and BSRR are reserve bit line selection lines, BL0 through BL2 and BR0 through BR2 are original bit lines, BLR and BRR are reserve bit lines, RDEC0 through RDEC3 are row decoders and WL0 through WL3 are word lines. In FIG. 3 which shows the circuit inside any one of the column decoders CDEC0 through CDEC2, Fi indicates a fuse.
Let us consider a situation where the addresses A1 is defective in the memory device of FIG. 2 with column decoders structured as shown in FIG. 3. In order to rescue the device, the fuse F0 inside the column decoder CDEC0 is cut first to inactivate the bit line selection line BSL0, the bit line selection circuit SL0 and the bit line BL0 connected to the column decoder CDEC0, and the address A1 is thereafter programmed into the redundant column decoder CDECR. In this manner, the defective bit address A1 is effectively replaced by the address A1' on the reserve bit line BLR.
In this situation, however, the bit with address A2 which is not assumed to be defective also becomes unusable simply because it is selected by the same column decoder CDEC0. Thus, it becomes necessary to also replace the address A2 by A2'. In other words, an extra redundancy circuit is used up wastefully because of the aforementioned unnecessary address replacement. If the address A3 were also defective in addition to the address A1, therefore, two sets of redundancy circuits such as reserve column decoders CDECR, etc. become necessary. An increased number of redundancy circuits means an increase in the chip area.